This invention relates to a semiconductor memory device which can constantly read out stored data thereby extending its function.
For a large capacity data storage, a semiconductor memory is used wherein data of a desired address is inputted or outputted through bit lines. With the recent trend toward digital signal processing for multi-functional purposes, a semiconductor memory is required which performs the function of constantly reading out a part of stored data without resort to or irrespective of address signals.
FIG. 1 shows part of the memory cells of a prior art semiconductor memory device. Each cell has a pair of multi-emitter transistors 101 and 102 with their base and collector connections mutually crossed, load resistors 103 and 104, and Schottky barrier diodes 117 and 118. A memory cell C1 of one bit is thus constructed, and the remaining memory cells C2, C3 and C4 have the same construction as the cell C1. A plurality of memory cells of the above construction, corresponding in number to the entire storage capacity, are arranged to constitute the memory device. The cells are connected to a positive word line 105 or 107 and to a negative word line 106 or 108. One emitter of one multi-emitter transistor and one emitter of the other multi-emitter transistor included in the respective cells are connected in common to a constant current source 119 or 120 via the negative word line 106 or 108. Each of the positive word lines 105 and 107 is connected to an address decoder so as to be set at a high potential during selection and at a low potential during non-selection. Bit lines 109, 110 and 111, 112 are respectively connected to constant current sources 113, 114 and 115, 116, and read/write data for a selected word is inputted to or outputted from these bit lines. A set of transistors 109' and 110' (or 111' and 112') are connected via the bit lines 109 and 110 (or 111 and 112) to the multi-emitter transistors 101 and 102 of each cell to cooperate therewith differentially.
The read operation of the memory device will now be described in respect of the memory cell C1, for example.
The word line 105 is first set at the high potential by the output of the address decoder and the bases of the transistors 109' and 110' are set at a reference potential V.sub.ref. Assuming now that the multi-emitter transistor 101 has been written with "H" (high logic) and the multi-emitter transistor 102 with "L" (low logic), the base potential of the multi-emitter transistor 101 is lower than V.sub.ref with the result that the current of the constant current source 113 is passed through the transistor 109'. The base potential of the transistor 102 is on the other hand higher than Vref, therefore the current of the constant current source 114 is passed through the multi-emitter transistor 102. In this manner, the information of the memory cell C1 can be read in terms of the collector currents of the transistors 109' and 110'.
The operation for writing "L" into the multi-emitter transistor 101 and "H" into the multi-emitter transistor 102 of the memory cell C1 is as follows.
When the base of the transistor 109' is applied with "L" which is lower than low level of the memory cell and the base of the transistor 110' with "H" which is higher than the high level of the memory cell under the application of the high potential to the word line 105, the current of the constant current source 113 is passed through the multi-emitter transistor 101 to decrease its collector voltage, thereby writing "L" into the multi-emitter transistor 101. At the same time, the current of the constant current source 114 is passed through the transistor 110' to urge the multi-emitter transistor 102 "OFF" so that the collector voltage of the transistor 102 is rendered high to write "H" into the multi-emitter transistor 102.
As described above, in the prior art memory device, stored data is read from the entire stored data onto the bit lines by the address signal. Therefore, to meet the aforementioned demand for constantly reading out part of the stored data irrespective of the address signals, a register file, independent of the memory, is used and data which has been written in the register file is constantly read out as the output thereof. In such a case, separate write control circuits are required for both the register and the memory, thus complicating the circuit construction of the whole device.